LIKE it or not, the post-desktop era is upon us, and microprocessor designers need to be ready, says John Hennessy, professor of electrical engineering at Stanford University. Hennessy made that point in the keynote address at the recent Micro-processor Forum in the US.

To get ready, designers should employ a combination of software-centric approaches and hardware-based techniques to try to break performance bottlenecks, according to Hennessy.

"There are advantages to both sides and somehow we need to understand how to put those advantages together," Hennessy says. "The challenge I give to all people thinking about working on uniprocessor architecture is to find a way to craft the best from these two approaches and put them together."

Current methods for squeezing performance out of processors through instruction level parallelism are losing effectiveness, he says, leading to what may be a major transition involving multithreading in software.

"Going into any new domain where we have to do some sort of multithreading requires the cooperation of the software guys," he says. "For some crazy reason, this industry has got it turned around to where it's faster to change hardware than it is to change software."

Hennessy's comments came as several vendors unveiled processors that employ multithreading techniques, among them Sun Microsystems, which announced the first implementation of its MAJC architecture, the MAJC 5200 chip. Sun has described the architecture as being aimed at high-powered multimedia applications, such as rendering a movie like Toy Story in real time.

Bill Joy, Sun's chief scientist, hinted at an interesting future of implementations for MAJC.

"Within the next decade, people will think a PC is something you carry in your pocket. It's a funny thing to have the solution before people know they have the problem," Joy says.

Joy says the chip already has inter-est from system manufacturers, though he refused to disclose who they are.

Tom Halfhill, embedded processor analyst with MicroDesign Resources, says the chip's floating point performance was higher than expected, leading him to wonder what kind of product it might land in.

"The customer must be needing this for some game or for a graphics-intense multimedia application, but not just a standard set-top box. I'm kind of puzzled," Halfhill says. "It's hard for me to believe it's going to be just another video game console."

Other design plans rolled out at the forum included new parts from IBM in both the 64-bit and embedded space. The Power4, set to debut in 2001, will boast 170 million transistors and will debut at a clock speed of 1GHz. Big Blue also detailed plans for the PowerPC 440.

Compaq Computer also detailed plans for its Alpha architecture, acquired through its purchase of Digital Equipment Corporation. The EV8, due in 2002, will run at speeds of 1.2 GHz and 2 GHz and will employ a symmetrical multithreading technique that the company claims adds only 5% to the size of the chip.

Arik Hesseldahl

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